1. Field of the Invention
The present invention relates to a nonvolatile memory, and particularly, to a technique of improving the writing speed of a nonvolatile memory.
2. Description of Related Art
Nonvolatile memories such as flash memories are generally provided with an automatic write function that controls, in response to a write command involving a write address and data, an internal power source, decoders, and a sense amplifier in a chip, to automatically conduct writing and write verification.
FIG. 8 is a flowchart showing a write process of a nonvolatile memory according to a related art. A write command is input to start an internal sequence. First, it is determined whether or not a write target address is in a write-protect state (step S101). If the target address is write-protected, the process ends. If the target address is writable, a write setup is conducted (step S102). Thereafter, a write operation is carried out (step S103). In the write operation, a target cell is selected through decoders, and a write voltage is applied to the target cell to write data therein. Then, a verify setup is carried out (step S104). The verify setup switches an internal voltage from a write level to a verify read level. A verify read operation is conducted to see if information written in the target cell agrees with the write data that should be written in the target cell (step S105). If the verification succeeds, the process ends. If the verification fails, the write data is set (step S106), and the flow returns to step S102 to again write the data. These steps form an automatic write sequence.
FIG. 9 is a view explaining bias conditions of a memory cell 10 in which hot electrons are written. Between a drain 12 and a source 14 of the memory cell, a voltage of about 5 V is applied, and a voltage of 10 V is applied to a gate 16 of the memory cell. This results in passing a large current 18 through a channel and drawing hot electrons 20 to a floating gate by an electric field between the gate and the channel, thereby achieving a write operation. If the memory cell is designed to represent “1” with an erased state, writing “0” in the memory cell is achieved by applying 5 V to the drain thereof and writing “1” in the memory cell is achieved by opening the drain thereof.
A related art disclosed in Japanese Patent Laid Open Publication (Kokai) No. 2001-135086 (FIG. 1) aims to shorten a memory write time and reduce power consumption. This related art carries out a write operation for a plurality of addresses that are randomly input, without turning on and off a step-up power source, to thereby reduce power consumption.
A related art disclosed in Japanese Patent Laid Open Publication (Kokai) No. 2000-243095 (FIG. 1) sequentially selects a plurality of memory cells in a memory and writes data therein. To shorten a write time any temperature conditions, the related art divides the memory cells into first and second groups and sets a first write condition of voltage and voltage applying time. Under this condition, the related art sequentially selects, writes, and verifies the memory cells of the first group. According to a time spent for writing all memory cells of the first group, the voltage and voltage applying time are changed to a second write condition. Under the second write condition, the memory cells of the second group are sequentially selected, written, and verified.
These related arts, however, pass a large current to conduct a write operation, and therefore, have a limitation in the number of cells that are collectively selected and written. One reason of this limitation is the current supply capacity of an internal electric potential controller that generates a step-up electric potential for the write current. Another reason is a potential float occurring at the source of a memory cell due to the large current passing therethrough. As the capacity of a memory chip increases, the problem of an increase in a total write time for the chip becomes more serious.